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A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator

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7 Author(s)
Nakamura, K. ; Microelectron. Res. Lab., NEC Corp., Kanagawa, Japan ; Kuhara, S. ; Kimura, T. ; Takada, M.
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This 512 Kw×8 b×3 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator and a 0.4-μm BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Newly developed circuit technologies include: 1) a zig-zag double word-line scheme, 2) a centered bit-line load layout scheme, and 3) a phase-locked-loop (PLL) with a multistage-tapped ring oscillator which generates a clock cycle proportional pulse (CCPP) and a clock edge lookahead pulse (CELP)

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 11 )

Date of Publication:

Nov 1994

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