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A suggestion for accelerating the analog fault simulation

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3 Author(s)
W. Vermeiren ; Fraunhofer-Inst. fur Integrierte Schaltungen, Erlangen, Germany ; B. Straube ; G. Elst

On the assumption that a commercial analog simulation tool is used an accelerated analog fault simulation can be carried out by simultaneous simulations of several faulty networks using external user written programs. If clusters with faults having similar sensitivity and temporal effects to the output can be constructed and when the faults of each cluster are simulated simultaneously a further speed-up can be achieved

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994