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Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

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4 Author(s)
Greiner, A. ; Lab. MASI, Univ. Pierre et Marie Curie, Paris, France ; Lucas, L. ; Wajsburt, F. ; Winckel, L.

This paper presents the design flow for a superscalar VLIW microprocessor using the 0.8 μ CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A full set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle and to maintain a high level of integration and performance. The final circuit contains about 875000 transistors with a die size of 14.6×14.6 mm2. The chip design and verification have been performed with new advanced CAD tools developed in the IDPS project. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994

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