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Logic synthesis and verification of the CPU and caches of a mainframe system

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5 Author(s)
Nguyen, H.N. ; Dept. of Design Methodology, BULL SA, Les Clayes-sous-Bois, France ; Tual, J.P. ; Ducousso, L. ; Thill, M.
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This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994