Delay reduction by segment substitution

This paper presents a new algorithm for reducing the delay of combinational circuits by structural modifications. Delay reduction is obtained by substituting delay-inefficient segments of the longest path in the circuit, by faster segments which perform the same function. Experimental results with the ISCAS85 benchmark circuits showed good delay reduction with only moderate area increase. Extension of this method for delay reduction of technology-mapped circuits appears to be feasible.<
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