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A low cost BIST methodology and associated novel test pattern generator

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3 Author(s)
Lin, S.-P. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Gupta, S.K. ; Breuer, M.A.

The area overhead and performance degradation associated with the hardware used to make a circuit testable using the conventional BILBO methodology can often be excessive. This paper presents a new BILBO-oriented methodology, called Built-In test for Balanced Structure (BIBS), that significantly reduces the number of BILBO registers used in creating a testable circuit, and thus decreases the area overhead and performance degradation. The concept of k-step functionally testable circuits is introduced. When the BIBS methodology is employed, circuits under test are guaranteed to be 1-step functionally testable and thus a high fault coverage can be achieved. A novel test pattern generator design to achieve 1-step functional testability for the BIBS TDM is presented

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994