Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

A fragmented register architecture and test advisor for BIST

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Illman, R.J. ; ICL Corporate Systems ; Traynor, D.J.

This paper describes two new developments in the implementation of quasi-exhaustive BIST. These are a new architecture, in which a conventional LFSR/MISR is broken down into three separate elements, and a CAD “test advisor” which provides a fast check of BIST DFT rules and informs the chip designer how to configure the registers and LFSRs within a design. These two new developments are closely interdependent and give a major increase in DFT productivity when implementing BIST

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994