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A fragmented register architecture and test advisor for BIST

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2 Author(s)
R. J. Illman ; ICL Corporate Systems ; D. J. Traynor

This paper describes two new developments in the implementation of quasi-exhaustive BIST. These are a new architecture, in which a conventional LFSR/MISR is broken down into three separate elements, and a CAD “test advisor” which provides a fast check of BIST DFT rules and informs the chip designer how to configure the registers and LFSRs within a design. These two new developments are closely interdependent and give a major increase in DFT productivity when implementing BIST

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994