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Bug identification of a real chip design by symbolic model checking

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3 Author(s)
Chen, B. ; Fujitsu Digital Technol. Ltd., Yokohama, Japan ; Yamazaki, M. ; Fujita, M.

We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994

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