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Implementation of a CORDIC processor for CFFT computation in gallium arsenide technology

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2 Author(s)
Sarmiento, R. ; Centro de Microelectron. Aplicada, Univ. de Las Palmas de Gran Canaria, Spain ; Eshraghian, K.

In this paper the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.8 μm gallium arsenide technology is presented. The processor is based upon the CORDIC algorithm in which elementary functions use only add and shift operations instead of the more conventional multiply and add hardware. In this architecture functional primitives were designed and extensively simulated taking into account process variations and in particular up to ±3σ of threshold voltage variation. Issues pertaining to the design of a 1024 point CFFT processor with 16 bit data and operating up to 1 GHz are discussed

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994

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