By Topic

PLFP256 a pipelined Fourier processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
P. Coulomb ; ENSERG, Grenoble, France ; F. Pogodalla

This paper presents a fast Fourier transform ASIC designed to be used on a DSP expansion board for a PC. From specification to test all steps in the ASIC design were made by 3rd year engineering school students. This project formed part of the practical work of the ASIC design courses in the ENSIMAG/ENSERG Architecture Department. The final chip implements the direct and reverse FFT algorithms, external buses arbitration, host interface, converters and memory management. Running at 25 MHz, this 30000 transistor ASIC can perform realtime signal processing on 44 kHz sample rate audio signals

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994