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A VLSI implementation of parallel fast Fourier transform

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5 Author(s)
Vacher, A. ; TIMA Lab., CNRS, Grenoble, France ; Benkhebbab, M. ; Guyot, A. ; Rousseau, T.
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This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994