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A new BIST approach for delay fault testing

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2 Author(s)
Vuksic, A. ; Siemens AG, Munich, Germany ; Fuchs, K.

A new built-in self testing (BIST) method for the detection of delay faults is proposed. It is shown that all possible pattern pairs can be generated with a MISR using all input combinations. In order to reduce the test pattern set, deterministic delay test generation is used and a minimal set of input vectors is derived via clique covering. Experimental results show that by just using the all-0 and all-1 input vectors, the non-robust path delay fault coverage ranges from 85% to 100%

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994