By Topic

Synthesis of delay-verifiable two-level circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ke, W. ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; Menon, P.R.

We introduce a new type of delay test set, called a delay-verification test set, which detects the presence of any path delay fault(s) that can affect the timing of the circuit. Such test sets exist even for some circuits that are not completely delay testable. We provide necessary and sufficient conditions for delay-verifiable two-level circuits, which are less stringent than those for complete delay testability. We introduce a new type of test which is not a path delay fault test in the usual sense, but is necessary for verifying the temporal correctness of the circuit under test. A synthesis procedure for delay-verifiable two-level circuits is provided. Experimental data show that delay-verifiable implementations are generally more area-efficient than completely delay testable implementations

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994