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Synthesis of sequential machines with reduced testing cost

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1 Author(s)
Sying-Jyan Wang ; Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan

We present a synthesis procedure for easily testable sequential machines. Testing cost of circuits synthesized from this procedure is reduced, while the added hardware overhead is negligible. The procedure begins with a modification of a state transition graph of a finite state machine (FSM); eventually an easily testable circuit that behaves like the original FSM is synthesized. This result can be combined with previous researches on fully testable sequential circuits to synthesize fully and easily testable sequential machines

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994