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Transforming sequential logic in digital CMOS ICs for voltage and I DDQ testing

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1 Author(s)
Sachdev, M. ; Philips Res. Lab., Eindhoven, Netherlands

To ensure the functionality, quality and reliability of digital CMOS ICs, the conventional logic testing and IDDQ testing are recognized as absolute test requirements. However, some of the bridging defects in sequential circuits are not detected by IDDQ. Furthermore, for complex devices, even scan based logic testing can be expensive. In this paper, a new concept of transforming sequential logic into purely combinational logic is described. With the help of the proposed method complete sequential logic is voltage and IDDQ tested in four test vectors

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994

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