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An efficient router for 2-D field programmable gate array

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2 Author(s)
Yu-Liang Wu ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Marek-Sadowska, M.

In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994