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A method for reducing power consumption of CMOS logic based on signal transition probability

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2 Author(s)
Akita, J. ; Dept. of Electron. Eng., Tokyo Univ., Japan ; Asada, K.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of a 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994

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