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Probability analysis for CMOS floating gate faults

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3 Author(s)
Xue, H. ; Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands ; Di, C. ; Jess, J.A.G.

The electrical behavior of a floating gate MOS transistor is mask-topology-dependent, i.e. floating on different sites of interconnection may result in different fault behavior. In this paper, we present a net-oriented deterministic approach to compute the probability of different open faults on each net, by taking into account the process defect statistics and mask layout data. The open faults causing floating gates are classified into three types, i.e. (1) open causes floating gates of p-channel transistors, (2) open causes floating gates of n-channel transistors, and (3) open causes floating gates of both p-channel transistors and n-channel transistors. For each net the probabilities of floating gate faults (1), (2) and (3) are obtained. The results of the analysis can be used as guidelines for designing more reliable and testable circuits, adopting more accurate fault models, introducing effective testing strategies

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994