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Logic and fault simulation by cellular automata

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2 Author(s)
Yih-Lang Li ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Cheng-Wen Wu

We propose a massively parallel architecture to speed up logic and fault simulation. We use 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994