Referenced Items are not available for this document.
We propose a massively parallel architecture to speed up logic and fault simulation. We use 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS
Date of Conference: 28 Feb-3 Mar 1994
- Page(s):
- 552 - 556
- Meeting Date :
- 28 Feb 1994-03 Mar 1994
- Print ISBN:
- 0-8186-5410-4
- INSPEC Accession Number:
- 4682326
- Conference Location :
- Paris
- Digital Object Identifier :
- 10.1109/EDTC.1994.326820
- Product Type:
- Conference Publications
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