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Synthesis of self-testable controllers

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2 Author(s)
S. Hellebrand ; Inst. Comput. Structures, Siegen Univ., Germany ; H. -J. Wunderlich

The paper presents a synthesis approach for pipeline-like controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994