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Design of a real time geometric classifier

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4 Author(s)
Robert, M. ; Univ. Montpellier II, France ; Gorria, P. ; Miteran, J. ; Turgis, S.

Summary form only given. The authors present the design of a real time parallel processor for classification adapted to image processing. They propose a geometric classification method allowing the use of a large number of parameters and ensuring a high decision speed. In their classification approach, two phases have to be considered: the training phase, which partitions the attribute space in characterizable regions by using a set of upper and lower limits (hypercube), hence, this set of limits defines a stress polytope, such that all the points of a polytope belong to the same class; and the decision phase, which compares an attribute vector to a set of lower and upper limits, that is, the polytope limits. These comparisons are made in parallel and in a synchronous way on every limit, every polytope and every parameter in one clock cycle. This classification operator has been integrated in the form of a full custom circuit developed in a CMOS 1.2 μm process (area 29 mm2). This powerful processor ia able to classify a point in less than 100ns. A comparison with a standard cell and an FPGA implementation (Xilinx XC4005) is made : it is shown that taking into account the reprogramming facilities of the SRAM based FPGAs, it is possible to implement a flexible reconfigurable classifier in a field programmable gate array

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994