By Topic

Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
A. Abderrahman ; Dept. of Electr. and Comput. Eng., Ecole Polytech. de Montreal, Que., Canada ; B. Kaminska ; Y. Savaria

Digital and mixed circuits performance are affected and limited by the simultaneous switching power and ground noise. For accurately selecting the number of power/ground pins to overcome switching noise, it is very important to accurately estimate the worst case simultaneous switching power and ground noise. In this paper we propose a heuristic that helps to estimate this worst case

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994