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Distributed fault simulation for sequential circuits by pattern partitioning

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4 Author(s)
Wen Ching Wu ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung Len Lee ; Jwu E Chen ; Won Yih Lin

The authors target the pattern partitioning on the distributed fault simulation because the number of patterns can be reduced by a factor of n, the number of machines, and the faults detected by any machine can be dropped through the communication of the network. For a sequential circuit, there is dependence between test patterns. The state of the circuit depends on the previous patterns applied to the circuit. When the patterns are partitioned into several groups for distributed fault simulation, a sub-fault simulation process for each machine is needed to simulate the circuit into the same state of its previous machine in order to obtain the right results. Hence, in this work, each machine firstly performs the true value simulation with the patterns, which are performed the fault simulation by the previous machines. As the fault simulation is partitioned as above, the state of the good machine is the same as that of the normal fault simulation. A mathematical model is presented to predict the performance of this pattern-partitioning distributed fault simulation. The fault simulator used in is SEESIM, which is a fast sequential circuit fault simulator based on single event equivalence. The statistics of the speedup of the distributed fault simulation with 2000 random patterns and patterns generated by an ATPG, respectively, are shown. It is shown that the speedup ratio increases with the number of machines, and the speedup can exceed the number of machines for some circuits

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994