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A redefinable symbolic simulation technique for testability design rules checking

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4 Author(s)
M. Hirech ; Lab. MASI/CAO-VLSI, Univ. Pierre et Marie Curie, Paris, France ; O. Floret ; A. Greiner ; E. Rejouan

A new symbolic simulation technique for design for testability (DFT) rules checking is discussed. With this method symbolic values and transfer functions of gates are redefinable to allow an adaptability to different sets of rules

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994