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CMOS ternary dynamic NORA logic

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2 Author(s)
A. Herrfeld ; Kassel Univ. ; S. Hentschke

A new ternary dynamic NORA-technique TDN has been developed which needs neither a complex clocking scheme nor buffering between successive stages. The complete TDN circuits for a one-trit multiplier and a sum mod-3 operator are presented

Published in:

Electronics Letters  (Volume:30 ,  Issue: 17 )