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An analog memory integrated circuit for waveform sampling up to 900 MHz

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2 Author(s)
Haller, G.M. ; Linear Accel. Center, Stanford Univ., CA, USA ; Wooley, B.A.

The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-μm complementary metal oxide semiconductor (CMOS) process with polysilicon-to-polysilicon capacitors. The measured rms cell response variation in a channel after cell pedestal subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB

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Nuclear Science, IEEE Transactions on  (Volume:41 ,  Issue: 4 )