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An enhanced technique for simulating short-circuit power dissipation

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2 Author(s)
Yacoub, G.Y. ; California Univ., San Diego, CA, USA ; Ku, W.H.

A circuit-simulation technique which permits the measurement of the average short-circuit power dissipation component in integrated circuits using SPICE is presented. It is an extension of a previously presented scheme by S.M. King (see ibid., vol.21, no.5, p.889-91, 1986) which measures average power dissipation while circuits are being simulated. The extended technique is most appropriate for low-power circuit design. It can be applied effectively to any complementary circuit structure, such as CMOS, that does not permit current flow (other than leakage current) during steady-state operation. Results for differently Wp/Wn ratioed W p/Wn CMOS circuits are shown

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 3 )

Date of Publication:

Jun 1989

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