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Current-limited switch-level timing simulator for MOS logic networks

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3 Author(s)
Genhong Ruan ; Fac. of Eng., Waterloo Univ., Ont., Canada ; Vlach, Jiri ; Barby, J.A.

An algorithm for switch-level timing simulation of MOS logic networks is proposed. The event-driven simulator, WATSWITCH, partitions the circuit into subblocks which are solved by replacing each transistor by a special current-limited switch. Because of the choice of the switch model, time-domain responses are obtained without model evaluations during the simulation, without table lookup, and without time-domain integration. This is achieved by allowing only capacitors and piecewise-constant current sources to be the elements of the simulator. Because resistors are not allowed, the time responses are known to be piecewise-linear segments. As a consequence, neither numerical integration nor transistor model evaluation is needed during the simulation

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:7 ,  Issue: 6 )