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Parametric yield optimization for MOS circuit blocks

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3 Author(s)
D. E. Hocevar ; Texas Instrum., Inc., Dallas, TX, USA ; P. F. Cox ; P. Yang

Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs. The first is based on quasi-Newton methods and utilizes the gradient of the yield. A novel technique for computing this yield gradient is derived and algorithms for its implementation are discussed. Geometrical considerations motivate the second method which formulates the problem in terms of a minimax problem. Both yield optimization techniques utilize transient sensitivity information from circuit simulations. Encouraging results have been obtained thus far; several circuit examples are included to demonstrate these techniques

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:7 ,  Issue: 6 )