A very-high-slew-rate CMOS operational amplifier

The amplifier uses a circuit to inject an extra bias current into a conventional source-coupled CMOS differential input stage in the presence of large differential input signals. This measure substantially increases the slew rate of an operational amplifier for a given quiescent current. The performance of the amplifier is compared to a conventional operational amplifier when used in a sample-and-hold circuit. The maximum operating clock frequency of the sample-and-hold increases from 290 kHz to 1 MHz with a hold capacitor of 1 nF. The amplifier has been fabricated in a 5- mu m CMOS process and dissipates a static power of 7.5 mW.<
>