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A content addressable memory management unit with on-chip data cache

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8 Author(s)
A. K. Goksel ; AT&T Bell Lab., Holmdel, NJ, USA ; R. H. Krambeck ; P. P. Thomas ; M. -S. Tsay
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The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 μm twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set

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IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 3 )