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High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment

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4 Author(s)
J. Kernhof ; Inst. for Microelectron., Stuttgart, West Germany ; M. A. Beunder ; B. Hoefflinger ; W. Haas

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 3 )