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Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm

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4 Author(s)
M. Verleysen ; Lab. of Microelectron., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium ; B. Sirletti ; A. M. Vandemeulebroecke ; P. G. A. Jespers

An implementation of a VLSI fully interconnected neural network with only two binary memory points per synapse is described. The small area of single synaptic cells allows implementation of neural networks with hundreds of neurons. Classical learning algorithms like the Hebb's rule show a poor storage capacity, especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connection; an algorithm for programming a Hopfield neural network as a high-storage content-addressable memory is proposed. The storage capacity obtained with this algorithm is very promising for pattern-recognition applications

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 3 )