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Design and test of memory management unit and cache controller chip

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2 Author(s)
D. Hsieh ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Feipei Lai

A design and test of memory management unit and cache controller (MMU/CC) chip for the Multiprocessor Architecture Reconciling Symbolic with numerical processing (MARS) are presented in this paper. MMU/CC can provide the memory access requirement of the MARS system for one load per cycle in the absence of cache miss, TLB miss, exception or interrupt. Not only the cache and memory operations are supported, but also an invalidation cache coherence protocol is embedded. The MMU/CC chip has 66290 transistors and 144 pins. The die size is 8653 /spl mu/m * 7114 /spl mu/m. We take a detailed look at critical issues of the design trade-offs, floor-planning, and testing.<>

Published in:

TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on  (Volume:1 )

Date of Conference:

19-21 Oct. 1993