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A 50 V, 0.56 m Omega cm2 vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering the gate sheet resistance compared with the conventional heavily doped n+-polysilicon gates. Devices with cell density as high as 8 million cells/inch2 and die size as large as 200 mil*220 mil and capable of conducting more than 160 A of current have been successfully fabricated with excellent gate yield. These results represent the highest reported forward conductivities for any type of power FET in the 50 V reverse blocking range.
Date of Publication: 8 June 1989