Referenced Items are not available for this document.
A 50 V, 0.56 m Omega cm2 vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering the gate sheet resistance compared with the conventional heavily doped n+-polysilicon gates. Devices with cell density as high as 8 million cells/inch2 and die size as large as 200 mil*220 mil and capable of conducting more than 160 A of current have been successfully fabricated with excellent gate yield. These results represent the highest reported forward conductivities for any type of power FET in the 50 V reverse blocking range.
Published in:
Electronics Letters
(Volume:25
,
Issue:
12
)
Date of Publication: 8 June 1989
- Page(s):
- 784 - 785
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 3455405
- Digital Object Identifier :
- 10.1049/el:19890529
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 8 June 1989
- Sponsored by :
- Institution of Engineering and Technology
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