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Allocation of multiport memories in data path synthesis

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5 Author(s)
M. Balakrishnan ; Dept. of Electr. Comput. Eng., Syracuse Univ., NY, USA ; A. K. Majumdar ; D. K. Banerji ; J. G. Linders
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An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:7 ,  Issue: 4 )