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An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example
Published in:
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
(Volume:7
,
Issue:
4
)
Date of Publication: Apr 1988
- Page(s):
- 536 - 540
- ISSN :
- 0278-0070
- INSPEC Accession Number:
- 3180623
- Digital Object Identifier :
- 10.1109/43.3188
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1988
- Sponsored by :
- IEEE Council on Electronic Design Automation
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