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Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique

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6 Author(s)
Aoyagi, M. ; Electrotech. Lab., Tsukuba, Japan ; Hamazaki, Y. ; Nakagawa, H. ; Kurosawa, I.
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A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed.<>

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Applied Superconductivity, IEEE Transactions on  (Volume:4 ,  Issue: 3 )