By Topic

High-performance vertical-power DMOSFETs with selectively silicided gate and source regions

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
K. Shenai ; General Electric. Corp. Res. & Dev., Schenectady, NY, USA ; P. A. Piacente ; C. S. Korman ; B. J. Baliga

A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the device's on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi/sub 2/ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Omega cm/sup 2/ for devices capable of blocking 50 V in the off state.<>

Published in:

IEEE Electron Device Letters  (Volume:10 ,  Issue: 4 )