Low-frequency noise and DC characterization of ionization damage in a 1-μm SOI CMOS technology adapted for space applications

The hardening of a standard 1-μm double layer metal CMOS SOI technology to a space environment is discussed. It is shown that a 50 krad(Si) hardened technology with VLSI performance can be obtained by changing a few steps in the basic process flow. Optimal results are obtained for a 850°C gate oxidation, combined with MESA-LOCOS isolation. Results of the radiation tests, using a ⁶⁰Co source, indicate changes in the threshold voltage of about 100 mV for a total dose of 100 krad(Si) and hole trapping factors in the range of 0.10-0.15. The increase in the low-frequency noise observed after irradiation is mainly related to the edge region of the MOS transistors