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Some design issues in multi-chip FPGA implementation of DSP algorithms

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2 Author(s)
Saha, A. ; Dept. of Electr. & Comput. Eng., Mississippi State Univ., MS, USA ; Krishnamurthy, R.

Field programmable gate arrays (FPGAs) provide an innovative and flexible platform to implement and evaluate digital signal processing (DSP) applications. A CAD design methodology which is used to implement DSP algorithms is presented. An introduction is given to the various issues involved in the multi-chip partitioning of large DSP implementations, and approaches towards efficient auto-partitioners are also discussed in detail. The design and implementation of an 8-point 1D discrete cosine transform (DCT) and its inverse (IDCT) on a processor with FPGAs is presented in this paper, as an illustrative example of a typical DSP algorithm. The processor uses 16-bit precision, is implemented on six Xilinx 4000 type FPGAs and operates at 40 MHz

Published in:

Rapid System Prototyping, 1994. Shortening the Path from Specification to Prototype. Proceedings., Fifth International Workshop on

Date of Conference:

21-23 Jun 1994