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On the design and implementation of a wafer yield editor

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2 Author(s)
de Gyvez, J.P. ; Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands ; Jess, J.A.G.

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and is able to predict wafer yields via simple simulation tools. An analysis approach based on site yields makes the system independent of the product and of the technology. The analysis technique makes it possible to investigate the effects of both correlated and uncorrelated sources of yield loss. The statistical information obtained can be used to study changes in the technological process. Graphical displays in the form of wafer maps are used to represent the spatial distribution of dice in the wafer. Capabilities for such as radial and angular distribution analyses, among others, are provided to examine data, and hypothetical wafer maps are created to visualize and predict simulated wafer yields

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:8 ,  Issue: 8 )