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On implementing large fault-tolerant binary tree architecture in WSI

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1 Author(s)
Siu-Cheung Chau ; Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta., Canada

A new layout scheme for fault-tolerant binary tree architecture in WSI with a high area utilization, short propagation delay, and short edge length is proposed. In the new layout scheme, the binary tree is partitioned into fault-tolerant modules. Each module can contain 3 active processors and k spares. That is, each fault-tolerant module can be connected to 4 other fault-tolerant modules. The new scheme can also be used to provide area efficient layout for previously proposed fault-tolerant binary tree architectures

Published in:

Computing and Information, 1993. Proceedings ICCI '93., Fifth International Conference on

Date of Conference:

27-29 May 1993