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Limitations of switch level analysis for bridging faults

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3 Author(s)
Rajsuman, R. ; Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA ; Malaiya, Y.K. ; Jayasumana, A.P.

Switch-level models are widely used for fault analysis of MOS digital circuits. Switch-level analysis (SLA) provides significantly more accurate results compared to gate-level models, and also avoids the complexities of circuit-level analysis. The accuracy of SLA is critically examined, and conditions under which SLA may generate incorrect results are specified. Such conditions may occur when the bulk of a transistor is connected to its source. These conditions are especially applicable under certain types of bridging faults. A simple technique is suggested for accurate switch-level modeling under such conditions

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:8 ,  Issue: 7 )

Date of Publication:

Jul 1989

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