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An asynchronous GaAs MESFET static RAM using a new current mirror memory cell

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2 Author(s)
A. Chandna ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; R. B. Brown

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm2 and cell current of 60 μA were achieved using a conventional E/D process

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 10 )