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A delay model and optimization method of a low-power BiCMOS logic circuit

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4 Author(s)
Shayan Zhang ; Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA ; Kalkur, T.S. ; Lee, S. ; Gatza, L.

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage

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Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 10 )