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Time-efficient VLSI artwork analysis algorithms in GOALIE2

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3 Author(s)
Chiang, K.-W. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Nahar, S. ; Chi-Yuan Lo

New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. The scanline algorithm virtually eliminates the redundant computation present in similar systems. It solves the VLSI layout analysis problem in O(n+k) expected time and O(√n) expected space, where n is the total number of input segments and k is the total number of intersection points. The new scanline algorithm is robust in what it will maintain its performance over a wide range of layout styles. Experimental results show that the running time is O(n1.0547), i.e. that these algorithms enable one to perform VLSI layout analysis in nearly linear time

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:8 ,  Issue: 6 )