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Testing for multiple faults in domino-CMOS logic circuits

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1 Author(s)
Jha, N.K. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA

The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-level model of the circuit. This results in the detection of all multiple faults having detectable consistent faults. The problem of test set invalidation due to arbitrary signal delays is easily taken care of in domino-CMOS circuits, making such an implementation of a function even more attractive than a fully complementary CMOS implementation, from the testability point of view

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:7 ,  Issue: 1 )