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Combinational circuit ATPG using binary decision diagrams

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4 Author(s)
Srinivasan, S. ; Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA ; Swaminathan, G. ; Aylor, J.H. ; Mercer, M.R.

The increasing size and complexity of current VLSI circuits has brought testing and design for testability into the mainstream of the design process. A significant amount of research has been done in the area of gate-level combinational ATPG using the stuck-at-fault model. The problem has been shown to be NP-complete and most of the current research attempts to find efficient ways to generate tests for hard faults in a reasonable amount of time on the average. Hence, there remains a lot of interest in the testing world for efficient techniques to do combinational ATPG. Use of ordered binary decision diagrams (OBDDs) for function representation has provided significant impetus to algebraic CAD techniques. This paper presents techniques for gate-level ATPG using OBDDs.<>

Published in:

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Date of Conference:

6-8 April 1993