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Parallelization methods for circuit partitioning based parallel automatic test pattern generation

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3 Author(s)
Klenke, R.H. ; Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA ; Williams, R.D. ; Aylor, J.H.

Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Parallel processing techniques can be applied to accelerate the process of finding test patterns. One problem with this approach is that most currently available distributed memory multicomputers have a limited amount of memory on each processor which limits the size of the circuit database that can be contained on a single node. Topological partitioning of the circuit database across several processors can increase the size of VLSI circuits that can be processed on a given parallel machine. This paper presents the architecture of a topologically partitioned ATPG system and several partitioning algorithms that can be used to partition the circuit-under-test. This paper also presents several parallelization methods that may be applied to topologically partitioned ATPG on a distributed memory multicomputer. Results of using these parallelization techniques along with topological partitioning are presented.<>

Published in:

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Date of Conference:

6-8 April 1993