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Classification of bridging faults in CMOS circuits: experimental results and implications for test

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2 Author(s)
Midkiff, S.F. ; Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA ; Bollinger, S.W.

Investigates linkages between physically realistic faults in CMOS integrated circuits and test generation and test quality. The procedure and results for an inductive fault analysis experiment that determined likely bridging faults in a set of CMOS circuits are presented. The implications of the results on test generation for physically realistic faults and on fault coverage are discussed.<>

Published in:

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Date of Conference:

6-8 April 1993